Integrated circuits (ICs) continue to become smaller as technology continues to improve. However, these improvements in technology have made leakage power an increasingly dominant component of total power dissipation. Leakage power has two main forms in modern IC processes: subthreshold leakage and gate leakage. Subthreshold leakage occurs due to a non-zero current in a transistor between its source and drain terminals when the transistor is in an OFF state. Gate leakage, on the other hand, occurs due to tunneling current through the gate oxide of a transistor. Both forms of leakage have increased, as a proportion of total power, due to changes necessitated by the improving technology. For example, with each process generation, supply voltages are reduced. In order to mitigate performance degradations due to the reduced supply voltage, transistor threshold voltages must also be reduced. Reducing threshold voltage, however, leads to an exponential increase in subthreshold leakage. Furthermore, gate oxides are thinned to improve transistor drive capability in advanced processes. This, however, leads to a considerable increase in gate leakage. Leakage power is a growing concern in CMOS design, and at least one recent study suggests that leakage power may constitute over 40% of total power for 70 nm technology.
A programmable logic device (PLD) is a well-known type of digital integrated circuit that can be programmed to perform specified logic functions. Examples of PLDs may include complex programmable logic devices (CPLDs), programmable logic arrays (PLAs), and programmable array logic (PAL) devices. One type of PLD, the field programmable gate array (FPGA), typically includes an array of configurable logic blocks (CLBs) and programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. Some FPGAs also include additional special-purpose circuit blocks (e.g., DLLs, RAM, multipliers, processors).
The CLBs, IOBs, interconnect, and other circuit blocks are typically programmed by loading a stream of configuration data (bitstream) into internal configuration memory cells that define how the CLBs, IOBs, interconnect, and other circuit blocks are configured. The configuration data can be read from memory (e.g., an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells in the FPGA then determine the function of the FPGA.
FPGAs are a popular choice for digital circuit implementation because of their flexibility, growing density and speed, short design cycle, and steadily decreasing cost. However, the programmability of FPGAs means that more transistors are typically needed to implement a given logic circuit, as compared with custom ASIC technologies. Since leakage power is proportional to total transistor count, leakage optimization is a key design objective in current and future FPGA technologies. Reducing the power consumption of FPGAs has many benefits, including lowering packaging/cooling costs, improving reliability, and enabling the use of FPGAs in low power applications (such as mobile electronics).
In contrast to ASICs, a circuit or function implemented on an FPGA typically uses only a fraction of the FPGA's total available resources. Leakage power, however, is dissipated in both the used and the unused portions of an FPGA. This further exacerbates the leakage power problem in FPGAS. In the used part of an FPGA, leakage can be categorized as either active mode or sleep (or standby) mode leakage power. Standby leakage power is that consumed in circuit blocks that are temporarily not in use and that have been put into a special “sleep” state, in which leakage is minimized. Active leakage power is consumed in circuit blocks that are “awake” (blocks that are in use).
Prior attempts to reduce and optimize leakage power have been concerned mainly with reducing standby leakage power. Some attempts to address active leakage power problems include raising the threshold voltage of transistors in non-critical paths or when high circuit performance (speed) is not needed, and replacing individual transistors with “stacks” of transistors coupled in series or with transistors having long channel lengths. Each of these previous leakage reduction techniques has an associated cost impacting circuit area, delay, and/or fabrication cost.
Therefore, a need exists for a method to reduce active leakage power with little or no cost.